FIG. 1 illustrates one type of prior art current mode DC/DC switching power supply, also known as a current mode DC/DC converter. Many other converter types, such as a switching voltage mode converter, can also benefit from the present invention. The type of converter shown in FIG. 1 is a peak current mode converter.
The operation of the converter is conventional and is as follows.
A clock (CLK) signal is applied to the set input of an RS flip-flop 20.
The setting of the RS flip-flop 20 generates a high signal at its Q output. A logic circuit 24, in response, turns transistor switch 26 on and turns the synchronous rectifier switch 28 off. Both switches may be MOSFETs or other types of transistors. A diode may replace the synchronous rectifier switch 28. The logic circuit 24 ensures that there is no cross-conduction of switches 26 and 28. The input voltage Vin applied to an inductor L1 through the switch 26 causes a ramping current to flow through the inductor L1, and this current flows through a low value sense resistor 32. The ramping current is filtered by an output capacitor 36 and supplies current to the load 38. The output capacitor 36 is relatively large to smooth out ripple.
The output voltage Vout is applied to a voltage divider 42, and the divided voltage is applied to the inverting input of a transconductance error amplifier 44. Capacitors may be connected across the resistors in the divider 42 to further compensate the feedback loop. A reference voltage Vref is applied to the non-inverting input of the amplifier 44. The output current of the amplifier 44 corresponds to the difference between the actual output voltage Vout and the desired output voltage. The voltage (a control voltage Vc) at a capacitor 46, connected to the output of the amplifier 44, is adjusted up or down based on the positive or negative current output of the amplifier 44. The control voltage Vc, among other things, sets the duty cycle of the switch 26, and the level of the control voltage Vc is that needed to equalize the inputs into the amplifier 44.
The control voltage Vc is applied to a comparator 50. The ramping voltage drop across the sense resistor 32, when the switch 26 is on, is sensed by a differential amplifier 52, having a certain gain, which outputs the voltage Visense. Many other ways are known to create the voltage Visense. When the voltage Visense exceeds the control voltage Vc, the comparator 50 is tripped to output a reset pulse to the RS flip-flop 20. This turns the switch 26 off and turns the synchronous rectifier switch 28 on to discharge the inductor L1, causing a downward ramping current. In this way, the peak current through the inductor L1 for each cycle is regulated to generate a desired output voltage Vout. The current through the sense resistor 32 includes a DC component (the lower frequency, average current) and an AC component (the higher frequency, ripple current).
FIG. 1 also illustrates a conventional slope compensation circuit 59, as is well known for current mode power converters. At high duty cycles (typically near or greater than 50%), the slope compensation circuit 59 ensures any duty cycle perturbations, such as caused by load current perturbations, are damped out. The slope compensation circuit 59 typically generates a ramping voltage that is subtracted from the control voltage Vc to create a downward ramping control voltage that is compared to the voltage Visense. The comparator 50 combines the control voltage Vc with the ramping voltage to create a compensated control voltage for comparison with the voltage Visense. The effect of the slope compensation circuit 59 is unrelated to the present invention.
The feedback voltage Vfb has ripple (at the switching frequency), and this ripple causes the control voltage Vc to have some ripple. This affects the accuracy of the tripping of the comparator 50.
FIG. 2 illustrates examples of the ramping voltage Visense, the rippling feedback voltage Vfb, the fixed reference voltage Vref, the rippling control voltage Vc (as a result of the constant Vref and rippling Vfb), and the average control voltage Vc (dashed line). The DC portions of Vfb, Visense, and Vc are not shown. The peak-to-peak ripple of the feedback voltage Vfb is just a small percentage of the nominal feedback voltage Vfb. The comparator 50 trips when the up-ramping voltage Visense crosses the control voltage Vc. Note that the comparator 50 trips earlier than had the control voltage Vc been a smoother voltage approximately equal to the average control voltage Vc. This may create an inaccuracy in the output voltage Vout. Further, for transient situations, where a large feedback voltage ripple is experienced, the error amplifier may operate out of its linear region, creating possible DC error due to asymmetrical up and down slew limits of the error amplifier. Still further, the ripple in the control voltage Vc may interact with the slope compensation function to cause variations in the duty cycle.
The various ripples may be lessened by adding capacitance to the output and to the control voltage Vc node, but increasing the capacitance reduces the gain-bandwidth product and thus reduces the converter's ability to react to transients.
What is needed is a technique for use in a switching converter that does not suffer from the drawbacks of the rippling feedback voltage Vfb and rippling control voltage Vc.